Introduction
Background of the Study
In the early 1970s, telephone calls didn’t instantly bounce between handheld devices and cell towers. Back then, the connection process required human operators to laboriously plug cords into the holes of a switchboard. Come 1974, a team of IBM researchers led by John Cocke set out in search of ways to automate the process. They envisioned a telephone exchange controller that would connect 300 calls per second (1 million per hour). Hitting that mark would require tripling or even quadrupling the performance of the company’s fastest mainframe at the time — which would require fundamentally reimagining high-performance computing.
The exchange controller project may have been canceled before it got off the ground, but the team’s underlying work led to the microprocessor architecture called RISC, for reduced instruction set computer. RISC enabled computers to complete tasks using simplified instructions, as quickly as possible. The goal to streamline hardware could be achieved with instruction sets composed of fewer steps for loading, evaluating and storing operations.
The new architecture enabled computers to run much faster than ever before. Its protocols, the foundation of computer evolution up to the present day, have affected everything from PCs and mobile devices to gaming and space travel. Just about all microprocessors derive from RISC architecture, and it is the basis of the multibillion-dollar UNIX systems market.
Significance of the Study
RISC Architecture:
An Overview MIPS RISC architecture delivers dramatic
cost/performance advantages over computers based on traditional architectures. This advantage is the result of a development methodology that demands optimization across many disciplines including custom VLSI, CPU organization, system-level architecture, operating system considerations, and compiler design. The trade-offs involved in this optimization process typify, and indeed are the essence of, RISC design.
Scope
RISC design is a methodology still somewhat in its infancy, enduring the usual growing pains as it strives for maturity. Because of the complexity of the subject and its dynamic state, a thorough and comprehensive discussion is beyond the scope of this book. A concise discussion of RISC is made more difficult by the nature of the design techniques — they involve myriad trade-offs and compromises between software/hardware, silicon area/compiler technology, component process technology/system software requirements, and so on. Therefore, this chapter provides only a brief overview of RISC concepts and their implementation so that the MIPS architecture can be better understood and appreciated. Architecture versus Implementation When discussing MIPS RISC products, an important distinction must be made between application architecture, and the hardware implementation of that architecture. For our purposes, the term application architecture refers to the instruction set, the physical components and timing, etc., to which all hardware implementations must adhere, and to which applications must limit themselves. Implementation refers to specific hardware designs using this application architecture, as presently embodied by the R-Series (R2000, R3000, R4000, and R6000) processors.
What Is RISC?
Historically, the evolution of computer architectures has been dominated by families of increasingly complex processors. Under market pressures to preserve existing software, Complex Instruction Set Computer (CISC) architectures evolved by the gradual accretion of microcode and increasingly elaborate operations. The intent was to supply more support for high-level languages and operating systems, as semiconductor advances made it possible to fabricate more complex integrated circuits. It seemed self-evident that architectures should become more complex as these technological advances made it possible to hold more complexity on VLSI devices. In recent years, however, Reduced Instruction Set Computer (RISC) architectures have implemented a much more sophisticated handling of the complex interaction between hardware, firmware, and software. RISC concepts emerged from statistical analysis of how software actually uses the resources of a processor. Dynamic measurement of system kernels and object modules generated by optimizing compilers show an overwhelming predominance of the simplest instructions, even in the code for CISC machines. Complex instructions are often ignored because a single way of performing a complex operation rarely matches the precise needs of high-level language and system environments. RISC designs eliminate the microcoded routines and turn the low-level control of the machine over to software.
MIPS RISC Architecture RISC Architecture An Overview
This approach is not new. But its application is more universal in recent years thanks to the prevalence of high-level languages, the development of compilers that can optimize at the microcode level, and dramatic advances in semiconductor memory and packaging. Itis now feasible to replace machine microcode ROM with faster RAM, organized as an instruction cache. Machine control then resides in the instruction cache and is, in effect, customized on the fly. The instruction stream generated by system- and compiler-generated code provides a precise fit between the requirements of high-level software and the capabilities of the hardware. Reducing or simplifying the instruction set is not the primary goal of the architectural concepts described here — it is a side effect of the techniques used to obtain the highest performance possible from available technology. Thus, the term Reduced Instruction Set Computers is a bit misleading: it is the push for performance
MIPS RISC Architecture Gerry Kane Joe Heinrich
Prentice Hall PTR, Upper Saddle River, New Jersey 07458 © 1992 MIPS Technologies, Inc.
The RiSC-16 is an 8-register, 16-bit computer. All addresses are short word addresses (i.e. address 0 corresponds to the first two bytes of main memory, address 1 corresponds to the second two bytes of main memory, etc.). Like the MIPS instruction-set architecture, by hardware convention, register 0 will always contain the value 0. The machine enforces this: reads to register 0 always return 0, irrespective of what has been written there. The RiSC-16 is very simple, but it is general enough to solve complex problems. There are three machine-code instruction formats and a total of 8 instructions
The RiSC-16 Instruction-Set Architecture ENEE 446: Digital Computer Design, Fall 2000 Prof. Bruce Jacob The RiSC-16 Instruction-Set Architecture ENEE 446: Digital Computer Design, Fall 2000 Prof. Bruce Jacob
Ond can find MIPS architecture in many modern systems. It’s often used in embedded systems like home routers, video game consoles, and digital TVs due to its efficiency and low power consumption. It’s also used in some supercomputers because of its high performance. you can find MIPS architecture in many modern systems. It’s often used in embedded systems like home routers, video game consoles, and digital TVs due to its efficiency and low power consumption. It’s also used in some supercomputers because of its high performance.
The popular Sony PlayStation I video game console used a MIPS R3000 RISC central processor.
Central Processing Unit:
(R3051) MIPS R3000A-Compatible 32-bit RISC Chip running at 33.8688 MHz
The chip is manufactured by LSI Logic Corp, with technology licensed from SGI
Operating Performance of 30 MIPS (Million Instructions Per Seccond)
Bus bandwidth 132 MB/s
4 KB Instruction Cache
1 KB non-associative SRAM Data Cache
2 MB of main RAM
Central Processing Unit:
(R3051) MIPS R3000A-Compatible 32-bit RISC Chip running at 33.8688 MHz
The chip is manufactured by LSI Logic Corp, with technology licensed from SGI
Operating Performance of 30 MIPS (Million Instructions Per Seccond)
Bus bandwidth 132 MB/s
4 KB Instruction Cache
1 KB non-associative SRAM Data Cache
2 MB of main RAM
Programming RISC-V Machine Code (Assembly Language)
RISC-V is not actually one instruction set, but it is a collection of instruction sets that in elementally build on top of each other. There are a set of baseline versions (common cores). Developers build on top of a common core by adding extensions. Given that the philosophy of RISC-V is to run on all kinds of machines, the notion of having different core ISAs and extensions aligns with it well.
RISC-V has three base versions: RV32, RV64 and RV128. The term RV is a short form 227 c Smruti R. Sarangi of RISC-V. The numbers 32, 64 and 128 indicate the bit width, respectively. The E su x has a special place. It indicates the embedded version that uses a reduced number of registers. For example, RV32E assumes only 16 integer registers as opposed to 32 integer registers in the regular version. It is important to note that unlike other ISAs (such as ARM Thumb), the instruction sizes remain the same. This simpli es compiler and processor design. Let us now focus on the extensions. Most versions of the ISAs support basic integer instructions.
They are thus named RV32I, RV64I and RV128I, respectively. Then, there are a bunch of extensions that can be added based on users requirements. The list of extensions has become quite large as of 2024 (around 20-30). Most of the common ones correspond to floating point instructions, atomic operations, cryptographic primitives, memory barriers, etc. For example, RV32IMA means that integer instructions (I), multiplication/ division instructions (M) and atomic instructions (A) are supported. These extensions themselves can have version numbers: a major version number and a minor version number. This is because the specifications keep changing as the ISAs are under development. For example, RV32I1p3 means that the major version number is 1 and the minor version is 3. The separator p is used to separate the major and minor version numbers. The extensions can be grouped into packages the same way we bundle together add-ons
The G su x that represents general-purpose computing, combines the base integer instruction set, additional integer instructions, oating point instructions and basic synchronization primitives. This is considered to be an essential set of instructions in a multi-core setup. RV32G is thus a general-purpose RISC-V ISA. It is so happening that the number of extensions is continuously increasing, and we are running out of letters !!!
This is why the Z series was introduced, where the extension name (su x) should start with Z and be followed by a word that describes the extension. For example, Zfa refers to additional floating point instructions. Let us now recall the fact that the embedded version of RISC-V does not reduce the in struction width; it instead reduces the number of available registers by 50%. On the lines of ARM Thumb, RISC-V does have a compressed format. In this case, the ISA special is C. In such contexts, most often we use the ISA RV32GC (general-purpose and compressed). The compressed instructions have the following limitations. The width of the instructions is 16 bits. Every compressed 16-bit instruction corresponds to a 32-bit RV32 instruction. They access a limited number of registers (typically limited to 8 registers in the 16-bit version). Limited opcode support. Immediate values that can be encoded are also commensurately smaller
Every computer must be able to perform arithmetic. The RISC-V assembly language notation add a, b, c instructs a computer to add the two variables b and c and to put their sum in a. This notation is rigid in that each RISC-V arithmetic instruction performs only one operation and must always have exactly three variables. For example, suppose we want to place the sum of four variables b, c, d, and e into variable a. (In this section, we are being deliberately vague about what a “variable” is;
The following sequence of instructions adds the four variables: add a, b, c
// The sum of b and c is placed in a add a, a, d
// The sum of b, c, and d is now in a add a, a, e
// The sum of b, c, d, and e is now in a Thus, it takes three instructions to sum the four variables. The words to the right of the double slashes
(//) on each line above are comments for the human reader, so the computer ignores them. Note that unlike other programming languages, each line of this language can contain at most one instruction. Another difference from C is that comments always terminate at the end of a line. The natural number of operands for an operation like addition is three: the two numbers being added together and a place to put the sum. Requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple: hardware for a variable number of operands is more complicated than hardware for a fixed number. This situation illustrates the first of three underlying principles of hardware design
Thus far, we have focused on designing combinational and sequential digital circuits at the schematic level. The process of finding an efficient set of logic gates to perform a given function is labor intensive and error prone, requiring manual simplification of truth tables or Boolean equa tions and manual translation of finite state machines (FSMs) into gates. In the 1990’s, designers discovered that they were far more productive if they worked at a higher level of abstraction, specifying just the logical function and allowing a computer-aided design (CAD) tool to produce the optimized gates. The specifications are generally given in a hardware description language (HDL). The two leading hardware description lan guages are SystemVerilog and VHDL. SystemVerilog and VHDL are built on similar principles but have different syntax. Discussion of these languages in this chapter is divided into two columns for literal side-by-side comparison, with SystemVerilog on the left and VHDL on the right.
The arithmetic and logic unit The ALU features a bank of 16 registers with 32 bit words. Arithmetic and logical operations, represented by instructions, always operate on these registers. Data can be transferred between memory and registers by separate load and store instructions. This is an important characteristic of RISC architectures, developed between 1975 and 1985. It contrasts with the earlier CISC architectures (Complex instruction set): Memory is largely decoupled from the processor. A second important characteristic is that most instructions take a single clock cycle (25 MHz) for their execution. The exceptions are access to memory, multiplication and division.. More about this will be presented later. This single-cycle rule makes such processors predictable in performance. The number of cycles and the time required for executing any instruction sequence is precisely defined. Predictability is essential in all real-time applications.
References:
The RiSC-16 Instruction-Set Architecture ENEE 446: Digital Computer Design, Fall 2000 Prof. Bruce Jacob The RiSC-16 Instruction-Set Architecture ENEE 446: Digital Computer Design, Fall 2000 Prof. Bruce Jacob
MIPS RISC Architecture Gerry Kane Joe Heinrich
Prentice Hall PTR, Upper Saddle River, New Jersey 07458 © 1992 MIPS Technologies, Inc.