Background of the Study
Introduction
The early nineties were marked by a change in the fates of many popular CPUs. The once-leading 8-bit CPUs, such as the Z80 and 6502, were already out of spotlight and Motorola’s famous 68000, along with other 16-bit designs that enjoyed success in the late 80s, had become candidates for replacement. Even at this time in the PC world, Tanenbaum, in his celebrated debate with Torvalds, gave Intel’s x86 architecture only five more years until its demise from the home market.
At first, it may look as if technological development had hit a wall at this point. But there was a new wave of relatively unknown CPUs making their way into mainstream devices. Many of these designs had originated in academia, and so existed to prove particular sets of design ideas. Examples of novel CPUs of that era included:
MIPS: Adopted by Silicon Graphics Incorporated (targeting graphics workstations).
PowerPC: Adopted by Apple (targeting desktop publishing).
SPARC: Created by Sun Microsystems (targeting servers and business workstations).
All of these processors had something in common: They followed the Reduced Instruction Set Computer (RISC) discipline, which radically shifted how these chips had to be designed and programmed. One rule of RISC CPUs dictated that a single instruction can’t mix memory with register operations, allowing hardware designers to simplify the circuitry that executes instructions… and then enhance it with parallelism techniques.
MIPS Computer Systems originated from the eagerness of its founders (Stanford faculty) to turn their research into physical processors, something that Silicon Valley-based venture capitalists in the 80s were also anxious to invest in [1]. Their debuting CPU, the ‘MIPS R2000’, is considered the first commercial CPU to incorporate a RISC design; and it found a space in many UNIX workstations.
However, it wasn’t until 1987 that MIPS’ chips became a topic of conversation, all due to being adopted (and later acquired) by Silicon Graphics Incorporated (SGI) to power their equipment. SGI was an influential innovator in the computer graphics market, especially with the development of hardware-accelerated vertex pipelines, whose task was originally carried out by software (within the CPU). After the acquisition, SGI had a leading position in both CPU and graphics sectors.
Before the development of the PlayStation, MIPS switched to a business model based on IP licensing, where their CPU designs would be sold in the form of licenses, and licensees were then free to customise and manufacture the designs. Part of their offerings included the R3000A CPU, found in their low-end catalogue. Consequently, the R3000A wasn’t associated with the flagship lineup
Sony designed their audio and graphics chips in-house, but they still needed the leading chip that could drive those two. The selected CPU had to be powerful enough to show off the impressive capabilities of Sony’s chips, but also affordable to keep the console at a competitive price.
At the same time, LSI Logic (a semiconductor manufacturer) was a MIPS licensee that provided a ‘build-your-own’ CPU program for businesses. This service was referred to as CoreWare and it enabled clients to build their own CPU packages by choosing a series of building blocks [2]. Part of the CoreWare library included the ‘CW33300’ block, a CPU core derived from the LSI LR33300, an off-the-shelf CPU chip that LSI also commercialized.
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In the end, Sony commissioned LSI to build their CPU package. They chose the CW33000, changed some bits and combined it with other blocks to form the chip you find on the PlayStation’s motherboard.
Significance of the Study
The Operating Portion of PlayStation Semantics of the hardware
OS ROM A 512KB OS ROM is mounted in the PlayStation.
OS kernel and boot loader are stored in this ROM. Access to ROM is prohibited and addresses are not disclosed. CPU The PlayStation uses a customized CPU based on the R3000A, which is a 32-bit RISC CPU. The specifications are as below.
The D cache of the PlayStation is called a Scratch Pad. Fixed address areas may be accessed with the same block number as cache memory
Memory Management Memory Map The space handled by the program is called logic space. Logic space is expressed by a 32-bit address, and is mapped in multiplex in physical space. With the “C” language, it is accessed by using a long pointer.
I-Cache Effective/not effective is determined for the instruction cache (hereafter, I-cache) by the top 4-bits of logic space. Out of the segments that correspond to the above-mentioned memory device, I-cache is effective with A, B, P and Q, but is not effective with C and R. A segment is a block unit that is divided from the functional plane of the memory space in the R3000. Note that this differs from those of other CPUs (8086 series) CPU and Its Peripherals 2-5 PlayStation Hardware When I-cache is effective, instruction codes are read into I-cache by collating them in specific units. If the target instruction is present in I-cache during execution, memory access via the bus is not necessary. By this means, application execution speed is increased. I-cache is packaged in 1K words (4K bytes), and is 1-way mapped. In other words, logic space is divided into 4K-byte units, and these are mapped in multiplex on the I-cache.
D-Cache The D-cache is composed of a high-speed memory housed in the CPU. This has a scratchpad structure, and is mapped on the memory space as an “S” segment so that game programmers can access it. Both data and programs can be stored in this segment. However, it is not a subject for DMA transmission. Address Alignment R3000 requires strict address alignment. This must start from an address which is a multiple of 4 for word-length (4 bytes) data, and a multiple of 2 for half word-length (2 bytes) data.
Memory accesses (data store, data load, instruction fetch) that do not comply with this rule will cause address errors. Registers The R3000 registers can be broadly divided into General-purpose registers and Program counters. General-purpose Registers There are 32 32-bit general-purpose registers. Each register is assigned to a specific use by the compiler, as shown below. These registers must be operated in accordance with this assignment when in thread database operation or when developing in assembler.
The macros in the table are defined in asm.h. Items to be noted when using general-purpose registers and assignment contents are as shown below I-Cache Effective/not effective is determined for the instruction cache (hereafter, I-cache) by the top 4-bits of logic space. Out of the segments that correspond to the above-mentioned memory device, I-cache is effective with A, B, P and Q, but is not effective with C and R.
A segment is a block unit that is divided from the functional plane of the memory space in the R3000. Note that this differs from those of other CPUs (8086 series) CPU and Its Peripherals 2-5 PlayStation Hardware When I-cache is effective, instruction codes are read into I-cache by collating them in specific units. If the target instruction is present in I-cache during execution, memory access via the bus is not necessary. By this means, application execution speed is increased.
I-cache is packaged in 1K words (4K bytes), and is 1-way mapped. In other words, logic space is divided into 4K-byte units, and these are mapped in multiplex on the I-cache. D-Cache The D-cache is composed of a high-speed memory housed in the CPU. This has a scratchpad structure, and is mapped on the memory space as an “S” segment so that game programmers can access it.
Both data and programs can be stored in this segment. However, it is not a subject for DMA transmission. Address Alignment R3000 requires strict address alignment. This must start from an address which is a multiple of 4 for word-length (4 bytes) data, and a multiple of 2 for half word-length (2 bytes) data. Memory accesses (data store, data load, instruction fetch) that do not comply with this rule will cause address errors. Registers The R3000 registers can be broadly divided into General-purpose registers and Program counters.
General-purpose Registers There are 32 32-bit general-purpose registers. Each register is assigned to a specific use by the compiler, as shown below. These registers must be operated in accordance with this assignment when in thread database operation or when developing in assembler. The macros in the table are defined in asm.h.
Chapter 1 : Object Orientated Programming Languages
The most commonly used PlayStation 1 Programming Language was C. Games became too big to be written in Assembly Language alone. C++ was too new for the industry at that time. Although there were exceptions to the rule, the industry standard was C.
On Systems before the PlayStation 1, developers would oft program their games in the system appropriate Assembly Language. At the beginning of the 1990s programs and projects got bigger and memory capacity increased. It was very daunting to write a program of that scope in the Assembly Language. With the C Programming Language, the development speed increased.
The Sony Playstation 1 had an R3000 MIPS RISC processor. The optimization you can get with Assembly is not too much, compared to the Amiga Motorola 68k or an ARM processor. The C compiler already generates well optimized code.
Portability was also a big consideration. You could compile C on almost any system available. Publishers wanted to bring their games on different platforms like Amiga (though declining), PC and consoles like the Playstation 1 or the Nintendo 64. C was the quasi industry standard at that time.
Another reason to use C was that Sony provided very good libraries for the system functions. This improved development speed even further. The SDK was easy to use and made the use of Assembly Language almost needless.
Exceptions to the Rule
Not every game was written entirely in C. One famous exception is Naughty Dog’s Crash Bandicoot from 1996. The Gameplay Logic is developed in LISP and C is only used for the system functions. Also, Forth was used sparingly. Some developers used script languages to develop logic. And despite the good SDK, some developers programmed graphics-related parts in Assembly Language.
One should also take into consideration that C itself was comparatively new for many teams. If they were used to Assembly, for instance, they would use it preferably.
The Playstation 1 and C++
There may be programs, or at least parts of programs, that are written in C++. But it had not that many proponents on the PSX as it hat on the PC at that time. There are many reasons for that.
At first, memory allocations were harder to keep down in C++ than in C. Then, C++ was too young for the industry. Very little development teams had real experience. And there was no internet as we know it today, with tutorials and videos. The advantages compared to C were too small. There was no STL or boost library. And last but not least the C++ compilers were slow.
The official Development Kit for the Playstation 1 was the PsyQ.
The game engines were mostly property of the teams that created them. It suited one or more projects for a studio but was not generalized like Unreal or Unity engines are today. For example, Andy Gavin from Naughty Dog created a game engine called “Game Oriented Object LISP 2” for Crash Bandicoot.
Despite its name, the Geometry Transformation Engine (GTE) is not a software engine for creating games. It is a Co-Processor that is attached to the main processor of the Playstation One. Its purpose is doing mathematical operations fast. It is also called Cop2 because it is the second Co-Processor.
By design it is ideal for mathematics that is required for calculations in 3D space. The main CPU is much slower in this specific task.
Mathematical Calculations in 3D space mainly consist of, but are not limited to:
3D Matrix Calculations (Rotation/Translation/Projection)
Lighting Calculations
Colour Calculations
MIPS Processor Architecture
MIPS Computer Systems designed the R3000 processor. It had RISC architecture and implemented the MIPS 1 Instruction Set Architecture. It was a 32 Bit processor and could operate at 20, 25 or 33.33 MHz.
RISC stands for Reduced Instruction Set Computers. This means that the instructions for the CPU are processed within one cycle. This reduces the number of instructions per cycle at the cost of a higher number of instructions per program. The opposite architecture is CISC (Complex Instruction Set Computer). Here the number of instructions per program is reduced, but the trade off is a lower number of instructions per processor cycle.
Although there was the possibility to use all kinds of programming languages, C dominated the PlayStation One. The reasons were portability, standardization and good support from the manufacturer Sony. C++ was on the horizon but at that time mainly used at the PC.