Introduction
Background of the Study
In the early 1970s, telephone calls didn’t instantly bounce between handheld devices and cell towers. Back then, the connection process required human operators to laboriously plug cords into the holes of a switchboard. Come 1974, a team of IBM researchers led by John Cocke set out in search of ways to automate the process. They envisioned a telephone exchange controller that would connect 300 calls per second (1 million per hour). Hitting that mark would require tripling or even quadrupling the performance of the company’s fastest mainframe at the time — which would require fundamentally reimagining high-performance computing.
The exchange controller project may have been canceled before it got off the ground, but the team’s underlying work led to the microprocessor architecture called RISC, for reduced instruction set computer. RISC enabled computers to complete tasks using simplified instructions, as quickly as possible. The goal to streamline hardware could be achieved with instruction sets composed of fewer steps for loading, evaluating and storing operations.
The new architecture enabled computers to run much faster than ever before. Its protocols, the foundation of computer evolution up to the present day, have affected everything from PCs and mobile devices to gaming and space travel. Just about all microprocessors derive from RISC architecture, and it is the basis of the multibillion-dollar UNIX systems market.
https://www.ibm.com/history/risc
Significance of the Study
RISC Architecture:
An Overview MIPS RISC architecture delivers dramatic
cost/performance advantages over computers based on traditional architectures. This advantage is the result of a development methodology that demands optimization across many disciplines including custom VLSI, CPU organization, system-level architecture, operating system considerations, and compiler design. The trade-offs involved in this optimization process typify, and indeed are the essence of, RISC design.
Scope RISC design is a methodology still somewhat in its infancy, enduring the usual growing pains as it strives for maturity. Because of the complexity of the subject and its dynamic state, a thorough and comprehensive discussion is beyond the scope of this book. A concise discussion of RISC is made more difficult by the nature of the design techniques — they involve myriad trade-offs and compromises between software/hardware, silicon area/compiler technology, component process technology/system software requirements, and so on. Therefore, this chapter provides only a brief overview of RISC concepts and their implementation so that the MIPS architecture can be better understood and appreciated. Architecture versus Implementation When discussing MIPS RISC products, an important distinction must be made between application architecture, and the hardware implementation of that architecture. For our purposes, the term application architecture refers to the instruction set, the physical components and timing, etc., to which all hardware implementations must adhere, and to which applications must limit themselves. Implementation refers to specific hardware designs using this application architecture, as presently embodied by the R-Series (R2000, R3000, R4000, and R6000) processors.
What Is RISC?
Historically, the evolution of computer architectures has been dominated by families of increasingly complex processors. Under market pressures to preserve existing software, Complex Instruction Set Computer (CISC) architectures evolved by the gradual accretion of microcode and increasingly elaborate operations. The intent was to supply more support for high-level languages and operating systems, as semiconductor advances made it possible to fabricate more complex integrated circuits. It seemed self-evident that architectures should become more complex as these technological advances made it possible to hold more complexity on VLSI devices. In recent years, however, Reduced Instruction Set Computer (RISC) architectures have implemented a much more sophisticated handling of the complex interaction between hardware, firmware, and software. RISC concepts emerged from statistical analysis of how software actually uses the resources of a processor. Dynamic measurement of system kernels and object modules generated by optimizing compilers show an overwhelming predominance of the simplest instructions, even in the code for CISC machines. Complex instructions are often ignored because a single way of performing a complex operation rarely matches the precise needs of high-level language and system environments. RISC designs eliminate the microcoded routines and turn the low-level control of the machine over to software.
MIPS RISC Architecture RISC Architecture An Overview This approach is not new. But its application is more universal in recent years thanks to the prevalence of high-level languages, the development of compilers that can optimize at the microcode level, and dramatic advances in semiconductor memory and packaging. Itis now feasible to replace machine microcode ROM with faster RAM, organized as an instruction cache. Machine control then resides in the instruction cache and is, in effect, customized on the fly. The instruction stream generated by system- and compiler-generated code provides a precise fit between the requirements of high-level software and the capabilities of the hardware. Reducing or simplifying the instruction set is not the primary goal of the architectural concepts described here — it is a side effect of the techniques used to obtain the highest performance possible from available technology. Thus, the term Reduced Instruction Set Computers is a bit misleading: it is the push for performance
MIPS RISC Architecture Gerry Kane Joe Heinrich
Prentice Hall PTR, Upper Saddle River, New Jersey 07458 © 1992 MIPS Technologies, Inc.
The RiSC-16 is an 8-register, 16-bit computer. All addresses are short word addresses (i.e. address 0 corresponds to the first two bytes of main memory, address 1 corresponds to the second two bytes of main memory, etc.). Like the MIPS instruction-set architecture, by hardware convention, register 0 will always contain the value 0. The machine enforces this: reads to register 0 always return 0, irrespective of what has been written there. The RiSC-16 is very simple, but it is general enough to solve complex problems. There are three machine-code instruction formats and a total of 8 instructions
Ond can find MIPS architecture in many modern systems. It’s often used in embedded systems like home routers, video game consoles, and digital TVs due to its efficiency and low power consumption. It’s also used in some supercomputers because of its high performance. you can find MIPS architecture in many modern systems. It’s often used in embedded systems like home routers, video game consoles, and digital TVs due to its efficiency and low power consumption. It’s also used in some supercomputers because of its high performance.
The popular Sony PlayStation I video game console used a MIPS R3000 RISC central processor.
Central Processing Unit:
(R3051) MIPS R3000A-Compatible 32-bit RISC Chip running at 33.8688 MHz
The chip is manufactured by LSI Logic Corp, with technology licensed from SGI
Operating Performance of 30 MIPS (Million Instructions Per Seccond)
Bus bandwidth 132 MB/s
4 KB Instruction Cache
1 KB non-associative SRAM Data Cache
2 MB of main RAM
Central Processing Unit:
(R3051) MIPS R3000A-Compatible 32-bit RISC Chip running at 33.8688 MHz
The chip is manufactured by LSI Logic Corp, with technology licensed from SGI
Operating Performance of 30 MIPS (Million Instructions Per Seccond)
Bus bandwidth 132 MB/s
4 KB Instruction Cache
1 KB non-associative SRAM Data Cache
2 MB of main RAM
References:
The RiSC-16 Instruction-Set Architecture ENEE 446: Digital Computer Design, Fall 2000 Prof. Bruce Jacob The RiSC-16 Instruction-Set Architecture ENEE 446: Digital Computer Design, Fall 2000 Prof. Bruce Jacob
MIPS RISC Architecture Gerry Kane Joe Heinrich
Prentice Hall PTR, Upper Saddle River, New Jersey 07458 © 1992 MIPS Technologies, Inc.